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DIGITAL ELECTRONICS interview questions

DIGITAL ELECTRONICS Ques 1. Explain about setup time and hold time, what will happen if there is setup time and hold tine violation, how to overcome this? Ans . For Synchronous flip-flops, we have special requirements for the inputs with respect to clock signal input there are Setup Time: Minimum time Period during which data must be stable before the clock makes a valid transition. E.g. for a positive edge triggered flip-flop having a setup time of 2ns so input data should be Stable for 2ns before the clock makes a  valid transaction from zero to one. Hold Time: Minimum time period during which data must be stable after the clock has made a valid transition. E.g. for a posedge triggered flip-flop, with a hold time of 1 ns. Input Data (i.e. R and S in the case of RS flip-flop) should be stable for at least 1 ns after clock has made transition from 0 to 1 Hold time is the amount of time after the clock edge that same input signal has to be held before changi...
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Digital Electronics Interview Questions

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Explain the difference between FIFO and RAM How to execute a full subtractor from a full adder? Define multiplexer Explain the difference between D flip-flop and a D latch? Explain two ways to convert a 2 input NAND gate an inverter? What happens when contents of a register are shifted left to right? How to implement an AND gate by using MUX? Name some of the applications of a buffer What is importance of cas and ras in SDRAM? Can you achieve 180 degree exact phase shift? How? How to determine longest path? How to determine maximum operating frequency? Explain the difference between one-hot and binary encoding? Explain the difference between moore and mealy state machines? How to develop a 4:1 MUX by using 2:1 MUX? Name two XOR gates among which one can function as buffer and the other as inverter? What is meant by waveform, and how to overcome it? Define is meant by glitch? Define slack Define skew. What are the issues associated with skew, and how to overcome th...
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Forthcoming Competitive Exams 2015

Government  Competitive Exams 2015 April ● National Defence Academy and Naval Academy Examination (I) 2015 (April 19) ● Rajasthan BSTC (General)/BSTC (Sanskrit) Entrance Exam., 2015 (April 19) ● Madhya Pradesh B.Ed. Entrance Exam., 2015 (April 19) ● Uttar Pradesh B.Ed. Joint Entrance Exam., 2015 (Conducted by Lucknow University) (April 25) ● Uttar Pradesh Public Service Commission Review Officer/Assistant Review Officer etc. (General/Special/Backlog) Recruitment Exam., 2014 (April 26) ● Chhattisgarh Pre-Engineering Test, 2015 (April 30) ● Indian Air Force Airmen [Group 'X' (Technical)/Group 'Y' (Non-Technical)] Recruitment Test (April-May) ● Himachal Pradesh State Eligibility Test, 2014 (April) May ● Uttar Pradesh Polytechnic Joint Entrance Exam., 2015 (May 3) ● Bihar Polytechnic Combined Entrance Exam., 2015 (May 3) ( Online Closing Date :  20 April, 2015) ● Uttarakhand Joint Entrance Exam. Polytechnic, 2015 (May 3-4) ● Bihar Para Medical-Dental/Para Medical (Interm...
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