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DIGITAL ELECTRONICS interview questions
DIGITAL ELECTRONICS Ques 1. Explain about setup time and hold time, what will happen if there is setup time and hold tine violation, how to overcome this? Ans . For Synchronous flip-flops, we have special requirements for the inputs with respect to clock signal input there are Setup Time: Minimum time Period during which data must be stable before the clock makes a valid transition. E.g. for a positive edge triggered flip-flop having a setup time of 2ns so input data should be Stable for 2ns before the clock makes a valid transaction from zero to one. Hold Time: Minimum time period during which data must be stable after the clock has made a valid transition. E.g. for a posedge triggered flip-flop, with a hold time of 1 ns. Input Data (i.e. R and S in the case of RS flip-flop) should be stable for at least 1 ns after clock has made transition from 0 to 1 Hold time is the amount of time after the clock edge that same input signal has to be held before changi...
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